000			02826cam a2200433Ma 4500
001			103724
005			20230411085610.0
008			040812s2004 ne a 001 0 eng d
010			_a 2004557408
035			_a(OCoLC)ocn300222546
040			_aRUQBL _bfre _cRUQBL _dOCLCQ _dDEBSZ
020			_a0750676043
020			_a9780750676045
029	1		_aDEBSZ _b11256772X
035			_a(OCoLC)300222546
049			_aGRAL
050	1	4	_aTK 7895 _bM463d 2004
082	0	0	_a621.39
100	1		_aMaxfield, Clive, _d1957-
245	1	4	_aThe design warrior's guide to FPGAs : _bdevices, tools and flows / _cClive "Max" Maxfield.
260			_aAmsterdam : _bNewnes/Elsevier, _cc2004.
300			_axvi, 542 p. : _bill. ; _c24 cm. + _e1 cédérom (12 cm.)
500			_aComprend un index. _5CaQTU
500			_aComprend des réf. bibliogr. _5CaQCU
500			_aComprend un index. _5CaQMUQET
505	0	0	_gCh. 1. _tIntroduction -- _gCh. 2. _tFundamental concepts -- _gCh. 3. _tThe origin of FPGAs -- _gCh. 4. _tAlternative FPGA architectures -- _gCh. 5. _tProgramming (configuring) an FPGA -- _gCh. 6. _tWho are all the players? -- _gCh. 7. _tFPGA versus ASIC design styles -- _gCh. 8. _tSchematic-based design flows -- _gCh. 9. _tHDL-based design flows -- _gCh. 10. _tSilicon virtual prototyping for FPGAs -- _gCh. 11. _tC/C++ etc.-based design flows -- _gCh. 12. _tDSP-based design flows -- _gCh. 13. _tEmbedded processor-based design flows -- _gCh. 14. _tModular and incremental design -- _gCh. 15. _tHigh-speed design and other PCB considerations -- _gCh. 16. _tObserving internal nodes in an FPGA -- _gCh. 17. _tIntellectual property -- _gCh. 18. _tMigrating ASIC designs to FPGAs and vice versa -- _gCh. 19. _tSimulation, synthesis, verification, etc. design tools -- _gCh. 20. _tChoosing the right device -- _gCh. 21. _tGigabit transceivers -- _gCh. 22. _tReconfigurable computing -- _gCh. 23. _tField-programmable node arrays -- _gCh. 24. _tIndependent design tools -- _gCh. 25. _tCreating an open-source-based design flow -- _gCh. 26. _tFuture FPGA developments -- _gApp. A. _tSignal integrity 101 -- _gApp. B. _tDeep-submicron delay effects 101 -- _gApp. C. _tLinear feedback shift registers 101.
650		6	_aRéseaux logiques programmables par l'utilisateur.
650		0	_aField programmable gate arrays.
650		4	_aMatrices de puertas programables.
650		4	_aPrimera Jornada de Catalogacion
653			_aApplication _aArchitecture _aCircuit _aFpga _aIntegre _aLogique _aMatrice _aPorte _aProgrammable _aReseau
653			_aUtilisateur _aSpecifique _aNumerique
655		6	_aMatériel didactique.
856	4	2	_3Description de l'ouvrage _uhttp://catdir.loc.gov/catdir/description/els051/2004557408.html
856	4	1	_3Table des matiéres _uhttp://catdir.loc.gov/catdir/toc/els051/2004557408.html
942			_2lcc _cbk
994			_aC0 _bDRFGD
946			_aJPR
999			_c104429 _d104429